Title: Physical Design Engineer
Duration: Fulltime
Location: Sunny Vale, CA
Description:
•RTL synthesis
•Tools: Genus (Synthesis), Innovous (PNR), Fusion Compiler (FC)
•Small flow (TCL/scripts) fixes/updates to unblock themselves.
•Timing closure (Internal, Interface)
•Place and Route (Able to create block closure recipe)
•Knowledge in all domains from RTL to GDS with Tcl and Perl scripting
•Worked on lower technologies like 16nm/10nm/7nm/5nm process.
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Must have worked in Synopsys and cadence tools for PnR &STA and Calibre for PV
•Block level implementation is requirement and chip level are good to have.
•Timing debug
•Good knowledge and debugging skills in Floor planning, Placement, CTS, and Routing
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